EC305N VLSI Design Lab
Course Name:
EC305N VLSI Design Lab
Programme:
B.Tech (ECE)
Semester:
Fifth
Category:
Programme Core (PC)
Credits (L-T-P):
(0-0-2) 1
Content:
Spice analysis of MOSFET input, output characteristics with parametric sweeps. Spice analysis of inverter (Ratioed logic families). Spice analysis of CMOS gates. Layout of CMOS gates, extraction and Spice analysis of extracted Layout of CMOS gates. Term Project (involves layout, LVS, switch level simulation
References:
Digital Integrated Circuits: A design perspective, (2 nd Edition), Jan M Rabaey, A Chandrakasan, B Nikolic, Pearson Education 2002.
CMOS Digital Integrated Circuits (3 rd ed.), Kang & Leblebici, Tata McGraw – Hill.
Principles of CMOS VLSI Design - A system perspective, (2 nd Edition) Neil H.E Weste and Kamran Eshraghian, Pearson Education
Department:
Electronics and Communication Engineering(ECE)