Kalpana G. Bhat

Assistant Professor Grade I

Tuesday, February 26, 2008

Total: 19 years, At MIT, Manipal : 12 years, At NITK: 13 years

Contact Details

kalpanabhat_ec[at]nitk[dot]ac[dot]in

kalps_bhats[at]yahoo[dot]com

0824-2473510(Office) 0824-2474510(Home)

Academic Background

• Ph.D. at NITK
• M.Tech., Karnataka University. Dharwad, 1999
• BE, UVCE, Bangalore University., 1994

Areas of Interest

Analog and Digital VLSI Design Mixed Signal Design

Significant Projects

Sponsored R & D Project (Seed money Grant) - 5 Lakhs Project

Title : Reconfigurable memory

Funding Agency/organization : Plan Fund, NITK

Significant Publications

Kalpana G Bhat, Tonse Laxminidhi and M. S. Bhat "Resolution Independent Fully Differential SCI Based SAR ADC Architecture Using Six Unit Capacitors" published on Sadhana letters, Acadamy Proceedings in Engineering Sciences, Springer July, 2020 (Published Online).
Kalpana G Bhat, T Laxminidhi and M. S. Bhat "A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture" published on IEEE Region 10 Asia Pacific Conference on Circuits and Systems and PrimeAsia ,2019 09 January 2020.
Prajnanam team at Micro electronics design centre (Karmic) Manipal. “Euclidean Distance Computation Algorithm for QAM applications” VDAT Conference, Bangalore, Jan 2006 and later Published in VSI Vision Journal, Dec.2006

Kalpana G Bhat, Adthya Nishad “A 0.5V SAR Analog to Digital Converter”, International Engineering Symposium (IES-2013), Kumamoto University, Japan, 4 - 6 March, 2013.

Pankaj Srivastav, Kalpana G bhat, Laxminidhi T., M.S Bhat “A 500KS/s 8 bit charge recycle based 2 bit per step SAR ADC”, 3rd International conf. on EAIT, ISI, Calcut. Dec 2012.

K. G. Bhat, T. Laxminidhi and M. S. Bhat, "An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC," TENCON 2015 - IEEE Region 10 Conference, Macao, 2015, pp. 1-6. doi: 10.1109/TENCON.2015

Kalpana G. Bhat, T. Laxminidhi and M S Bhat, "A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture", Sādhanā, Springer Publications, June 2019, 44: 137. https://doi.org/10.1007/s12046-019-1121-1

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